1. Field of the Invention
This invention relates generally to sigma-delta (ΣΔ) loops, and more particularly to a sample and hold (SAH) phase detector (PD) architecture and method of clocking to avoid quantization noise folding in ΣΔ loop applications such as a ΣΔ frequency synthesizer.
2. Description of the Prior Art
Conventional charge pump based phase detectors suffer several problems when they are used in ΣΔ loop applications. These problems may include, for example, noise folding due to non-linearity, charge/discharge mismatch, and the like.
In view of the foregoing, it is highly desirable and advantageous to provide a PD architecture and a PD clocking scheme that avoids quantization noise increases due to noise folding. It would be further advantageous if the PD architecture could provide an integrated filtering function.